摘要 :
In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can er...
展开
In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum.
收起
摘要 :
Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very ...
展开
Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose reversible gates are also shown.
收起
摘要 :
Reversible logic synthesis plays an important role in reversible computing. This paper proposes a novel algorithm for synthesizing reversible circuits in terms of PNC (Positive/Negative Control) gates. The algorithm is based on sw...
展开
Reversible logic synthesis plays an important role in reversible computing. This paper proposes a novel algorithm for synthesizing reversible circuits in terms of PNC (Positive/Negative Control) gates. The algorithm is based on switching two output minterms with only one different variable between them step by step until the original reversible function transforms to the identity function. We also give all the 3 input /output reversible functions, reporting distributions of circuit sizes. Through synthesizing several circuits which are used in other literatures, the experimental results show better performance in reducing the gate count, so as to decrease the cost of the network.
收起
摘要 :
Reversible logic synthesis plays an important role in reversible computing. This paper proposes a novel algorithm for synthesizing reversible circuits in terms of PNC (Positive/Negative Control) gates. The algorithm is based on sw...
展开
Reversible logic synthesis plays an important role in reversible computing. This paper proposes a novel algorithm for synthesizing reversible circuits in terms of PNC (Positive/Negative Control) gates. The algorithm is based on switching two output minterms with only one different variable between them step by step until the original reversible function transforms to the identity function. We also give all the 3 input /output reversible functions, reporting distributions of circuit sizes. Through synthesizing several circuits which are used in other literatures, the experimental results show better performance in reducing the gate count, so as to decrease the cost of the network.
收起
摘要 :
This paper proposes the use of Universal LOgic Gates (ULGs) as basic elements for masked programmable master-slices customizable by the topmost metal layer. This new approach called Maragata combines the efficiency of MPGAs with t...
展开
This paper proposes the use of Universal LOgic Gates (ULGs) as basic elements for masked programmable master-slices customizable by the topmost metal layer. This new approach called Maragata combines the efficiency of MPGAs with the fiexibility of FPGA architecture. Due to the intensive use of processor-like blocks in current VLSI circuits, ULGs were developed considering the implementation of sequential circuits. A set of ULGs were studied and designed for CMOS technology. Area comparison was accomplished by mapping various combinational and sequential circuits into ULGs master-slices and to a gate array master-silice called Agata. Results show that significant area gain and connection reduction can be achieved in this new approach.
收起
摘要 :
This paper proposes the use of Universal LOgic Gates (ULGs) as basic elements for masked programmable master-slices customizable by the topmost metal layer. This new approach called Maragata combines the efficiency of MPGAs with t...
展开
This paper proposes the use of Universal LOgic Gates (ULGs) as basic elements for masked programmable master-slices customizable by the topmost metal layer. This new approach called Maragata combines the efficiency of MPGAs with the fiexibility of FPGA architecture. Due to the intensive use of processor-like blocks in current VLSI circuits, ULGs were developed considering the implementation of sequential circuits. A set of ULGs were studied and designed for CMOS technology. Area comparison was accomplished by mapping various combinational and sequential circuits into ULGs master-slices and to a gate array master-silice called Agata. Results show that significant area gain and connection reduction can be achieved in this new approach.
收起
摘要 :
This paper investigates the role that the gate oxide thickness (Tox) plays on power and delay behaviors of logic circuits. Static and dynamic CMOS logic gates have been considered as benchmarks. To extend the predictive simulation...
展开
This paper investigates the role that the gate oxide thickness (Tox) plays on power and delay behaviors of logic circuits. Static and dynamic CMOS logic gates have been considered as benchmarks. To extend the predictive simulation study here presented to future technologies, Berkeley Predictive Technology Models (BPTM) have been used. From a circuit perspective, simulation results showed that the optimal Tox is larger than the nominal value, usually obtained from a device perspective.
收起
摘要 :
This paper investigates the role that the gate oxide thickness (Tox) plays on power and delay behaviors of logic circuits. Static and dynamic CMOS logic gates have been considered as benchmarks. To extend the predictive simulation...
展开
This paper investigates the role that the gate oxide thickness (Tox) plays on power and delay behaviors of logic circuits. Static and dynamic CMOS logic gates have been considered as benchmarks. To extend the predictive simulation study here presented to future technologies, Berkeley Predictive Technology Models (BPTM) have been used. From a circuit perspective, simulation results showed that the optimal Tox is larger than the nominal value, usually obtained from a device perspective.
收起
摘要 :
We have proposed gate architectures to perform NOR logic operations using the single electron transistors. The designs have been verified by using the SET-SPICE model and the nanostructure modeling software called SIMON. First, a ...
展开
We have proposed gate architectures to perform NOR logic operations using the single electron transistors. The designs have been verified by using the SET-SPICE model and the nanostructure modeling software called SIMON. First, a two-input NOR gate was designed and verified and then the design was extended to implement a NOR gate with three inputs.
收起
摘要 :
We have proposed gate architectures to perform NOR logic operations using the single electron transistors. The designs have been verified by using the SET-SPICE model and the nanostructure modeling software called SIMON. First, a ...
展开
We have proposed gate architectures to perform NOR logic operations using the single electron transistors. The designs have been verified by using the SET-SPICE model and the nanostructure modeling software called SIMON. First, a two-input NOR gate was designed and verified and then the design was extended to implement a NOR gate with three inputs.
收起
原文获取